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NCS2002, NCV2002 Sub-One Volt Rail-to-Rail Operational Amplifier with Enable Feature
The NCS2002 is an industry first sub-one volt operational amplifier that features a rail-to-rail common mode input voltage range, along with rail-to-rail output drive capability. This amplifier is guaranteed to be fully operational down to 0.9 V, providing an ideal solution for powering applications from a single cell Nickel Cadmium (NiCd) or Nickel Metal Hydride (NiMH) battery. Additional features include no output phase reversal with overdriven inputs, trimmed input offset voltage of 0.5 mV, extremely low input bias current of 40 pA, and a unity gain bandwidth of 1.1 MHz at 5.0 V. The NCS2002 also has an active high enable pin that allows external shutdown of the device. In the standby mode, the supply current is typically 1.9 mA at 1.0 V. Because of its small size and enable feature, this amplifier represents the ideal solution for small portable electronic applications. The NCS2002 is available in the space saving SOT23-6 (TSOP-6) package with two industry standard pinouts.
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1 TSSOP-6 SN SUFFIX CASE 318G
MARKING DIAGRAM
* * * * * * * * * * * * * * * * * *
0.9 V Guaranteed Operation Standby Mode: ID = 1.9 mA at 1.0 V, Typical Rail-to-Rail Common Mode Input Voltage Range Rail-to-Rail Output Drive Capability No Output Phase Reversal for Over-Driven Input Signals 0.5 mV Trimmed Input Offset 10 pA Input Bias Current 1.1 MHz Unity Gain Bandwidth at $2.5 V, 1.0 MHz at $0.5 V Tiny SOT23-6 (TSOP-6) Package Pb-Free Packages are Available Single Cell NiCd / NiMH Battery Powered Applications Cellular Telephones Pagers Personal Digital Assistants Electronic Games Digital Cameras Camcorders Hand Held Instruments
Rail to Rail Input Rail to Rail Output
AAxAYW G G 1 AA x= A Y W G = Device Code Marking Defined on Page 15 in Ordering Information = Assembly Location = Year = Work Week = Pb-Free Package
(Note: Microdot may be in either location)
Typical Applications PIN CONNECTIONS
VOUT VCC Non-Inverting Input 1 2 3 +- 6 5 4 VEE Enable Inverting Input
Style 1 Pinout (SN1T1)
VOUT VEE Non-Inverting Input
1 2 3 +-
6 5 4
VCC Enable Inverting Input
0.8 V to 7.0 V
+ -
Style 2 Pinout (SN2T1)
This device contains 81 active transistors.
ORDERING AND MARKING INFORMATION
See detailed ordering, marking, and shipping information in the package dimensions section on page 15 of this data sheet.
Figure 1. Typical Application
(c) Semiconductor Components Industries, LLC, 2007
January, 2007 - Rev. 6
1
Publication Order Number: NCS2002/D
NCS2002, NCV2002
MAXIMUM RATINGS
Rating Supply Voltage (VCC to VEE) Input Differential Voltage Range (Note 1) Input Common Mode Voltage Range (Note 1) Output Short Circuit Duration (Note 2) Junction Temperature Power Dissipation and Thermal Characteristics SOT23-6 Package Thermal Resistance, Junction-to-Air Power Dissipation @ TA = 70C Operating Ambient Temperature Range NCS2002 NCV2002 (Note 3) Storage Temperature Range ESD Protection at any Pin Human Body Model (Note 4) Symbol VS VIDR VICR tSc TJ Value 7.0 VEE - 300 mV to 7.0 V VEE - 300 mV to 7.0 V Indefinite 150 Unit V V V sec C
RqJA PD TA
235 340 -40 to 105 -40 to 125 -65 to 150 2000
C/W mW C
Tstg VESD
C V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Either or both inputs should not exceed the range of VEE - 300 mV to VEE + 7.0 V. 2. Maximum package power dissipation limits must be observed to ensure that the maximum junction temperature is not exceeded. TJTA + (PD RqJA) 3. NCV prefix is for automotive and other applications requiring site and change control. 4. ESD data available upon request.
DC ELECTRICAL CHARACTERISTICS (VCC = 2.5 V, VEE = -2.5 V, VCM = VO = 0 V, RL to GND, TA = 25C, unless otherwise noted)
Rating Input Offset Voltage VCC = 0.45 V, VEE = -0.45 V TA = 25C TA = 0C to 70C TA = -40 to +125C VCC = 1.5 V, VEE = -1.5 V TA = 25C TA = 0C to 70C TA = -40 to +125C VCC = 2.5 V, VEE = -2.5 V TA = 25C TA = 0C to 70C TA = -40 to +125C Input Offset Voltage Temperature Coefficient (RS = 50) TA = -40 to +125C Input Bias Current (VCC = 1.0 V to 5.0 V) Input Common Mode Voltage Range Large Signal Voltage Gain VCC = 0.45 V, VEE = -0.45 V RL = 10 k VCC = 1.5 V, VEE = -1.5 V RL = 10 k VCC = 2.5 V, VEE = -2.5 V RL = 10 k Output Voltage Swing, High State Output (VID = + 0.5 V) TA = Tlow to Thigh VCC = 0.45 V, VEE = -0.45 V RL = 10 k RL = 2.0 k VCC = 1.5 V, VEE = -1.5 V RL = 10 k RL = 2.0 k VCC = 2.5 V, VEE = -2.5 V RL = 10 k RL = 2.0 k Symbol VIO -6.0 -8.5 -9.5 -6.0 -7.0 -7.5 -6.0 -7.5 -7.5 DVIO / DT IIB VICR AVOL - - 10 VOH 0.40 0.35 1.45 1.40 2.45 2.40 0.442 0.409 1.494 1.473 2.493 2.469 - - - - - - 40 40 40 - - - V - - - 0.5 - - 0.5 - - 0.5 - - 8.0 10 VEE to VCC 6.0 8.5 9.5 6.0 7.0 7.5 6.0 7.5 7.5 - - - mV/C pA V kV/V Min Typ Max Unit mV
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DC ELECTRICAL CHARACTERISTICS (VCC = 2.5 V, VEE = -2.5 V, VCM = VO = 0 V, RL to GND, TA = 25C, unless otherwise noted)
Rating Output Voltage Swing, Low State Output (VID = - 0.5 V) TA = -40 to +125C VCC = 0.45 V, VEE = -0.45 V RL = 10 k RL = 2.0 k VCC = 1.5 V, VEE = -1.5 V RL = 10 k RL = 2.0 k VCC = 2.5 V, VEE = -2.5 V RL = 10 k RL = 2.0 k Common Mode Rejection Ratio (Vin = 0 to 5.0 V) Power Supply Rejection Ratio (VCC = 0.5 V to 2.5 V, VEE = -2.5 V) Output Short Circuit Current VCC = 0.45 V, VEE = -0.45 V, VID = $0.4 V Source Current High Output State Sink Current Low Output State VCC = 1.5 V, VEE = -1.5 V, VID = $0.5 V Source Current High Output State Sink Current Low Output State VCC = 2.5 V, VEE = -2.5 V, VID = $0.5 V Source Current High Output State Sink Current Low Output State Power Supply Current (Per Amplifier, VO = 0 V) TA = -40 to +125C VCC = 0.5 V to VEE = -0.5 V Venable = VCC Venable = VEE VCC = 1.5 V to VEE = -1.5 V Venable = VCC Venable = VEE VCC = 2.5 V to VEE = -2.5 V Venable = VCC Venable = VEE Enable Input Threshold Voltage (VCC = 2.5 V, VEE = -2.5 V) Operating Disabled Enable Input Current (VCC = 5.0 V, VEE = 0) Enable = 5.0 V Enable = GND Symbol VOL - - - - - - CMRR PSRR ISC 0.5 - 25 - 65 - ID - - - - - - Vth(EN) - 1.7 V + VEE - - 480 1.5 720 2.2 820 2.5 2.7 V + VEE 1.9 1.1 1.1 600 3.0 900 5.0 1000 5.0 2.8 V + VEE - 2.0 2.0 V 1.0 -3.0 32 -58 86 -128 - -2.0 - -45 - -100 mA 60 60 -0.446 -0.432 -1.497 -1.484 -2.496 -2.481 82 85 -0.40 -0.35 -1.45 -1.40 -2.45 -2.40 - - dB dB mA Min Typ Max Unit V
IEnable
mA
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AC ELECTRICAL CHARACTERISTICS (VCC = 2.5 V, VEE = -2.5 V, VCM = VO = 0 V, RL to GND, TA = 25C, unless otherwise noted)
Rating Differential Input Resistance (VCM = 0 V) Differential Input Capacitance (VCM = 0 V) Equivalent Input Noise Voltage (f = 1.0 kHz) Gain Bandwidth Product (f = 100 kHz) VCC = 0.45 V, VEE = -0.45 V VCC = 1.5 V, VEE = -1.5 V VCC = 2.5 V, VEE = -2.5 V Gain Margin (RL = 10 k, CL = 5.0 pf) Phase Margin (RL = 10 k, CL = 5.0 pf) Power Bandwidth (VO = 4.0 VPP, RL = 2.0 k, THD = 1.0 %, AV = 1.0) Total Harmonic Distortion (VO = 4.0 VPP, RL = 2.0 k, AV = 1.0) f = 1.0 kHz f = 10 kHz Slew Rate (VS = $2.5 V, VO = -2.0 V to 2.0 V, RL = 2.0 k, AV = 1.0) Positive Slope Negative Slope Time Delay for Device to Turn On (RL = 10 k) Time Delay for Device to Turn Off (RL = 10 k) Symbol Rin Cin en GBW Min - - - - - 0.6 - - - - - 0.85 0.85 - - Typ >1.0 3.0 100 0.8 0.8 0.9 6.5 60 80 0.008 0.08 1.2 1.3 5.5 2.5 Max - - - - - - - - - - - - - 7.5 3.0 Unit tera W pf nV/ Hz MHz
Am fm BWP THD
dB Deg kHz %
SR
V/ms
ton toff
ms ms
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0 Vsat, Output Saturation Voltage (mV) -200 -400 -600 600 400 200 0 100 Low State Output Sinking Current VEE 1.0 k 10 k 100 k 1.0 M High State Output Sourcing Current VS = 2.5 V RL to GND TA = 25C 0 Vsat, Output Saturation Voltage (V) -0.1 -0.2 -0.3 -0.4 -0.5 0.4 0.3 0.2 0.1 0 0 4.0 8.0 12 16 Low State Output Sinking Current VEE 20 VS = $2.5 V RL to GND TA = 25C VCC High State Output Sourcing Current
VCC
RL, Load Resistance (W)
IL, Load Current (mA)
Figure 2. Output Saturation Voltage versus Load Resistance
Figure 3. Output Saturation Voltage versus Load Current
10,000 1000 IIB, Input Current (pA) 100 10 1.0 0 0 25 50 75 100 125 TA, Ambient Temperature (C) VS = 2.5 V RL = CL = 0 AV = 1.0
100 80 AV, Gain (dB) 60 40 20 0 1.0 10 100 1.0 k 10 k 100 k 1.0 M Phase Gain VS = $2.5 V RL = 100 k TA = 25C Amp = 0.8 mV 0 20 60 100 140 180 10 M F, Excess Phase ()
f, Frequency (Hz)
Figure 4. Input Bias Current versus Temperature
Figure 5. Gain and Phase versus Frequency
VS = $2.5 V RL = 10 k CL = 10 pF AV = 1.0 TA = 25C 500 mV/Div t, Time (500 ns/Div) 50 mV/Div
VS = $2.5 V RL = 10 k CL = 10 pF AV = 1.0 TA = 25C
t, Time (1.0 ms/Div)
Figure 6. Transient Response http://onsemi.com
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Figure 7. Slew Rate
NCS2002, NCV2002
CMRR, Common Mode Rejection Ratio (dB) 10 8.0 6.0 4.0 2.0 AV = 1.0 RL = 10 k TA = 25C 90 80 70 60 50 40 30 20 10 0 10 100 1.0 k 10 k 100 k f, Frequency (Hz) 1.0 M 10 M VS = 2.5 V RL = AV = 1.0 TA = 25C
Vout, Output Voltage (Vpp)
VS = 3.5 V
VS = 2.5 V
VS = 0.45 V 10 k 100 k f, Frequency (Hz) 1.0 M
0 1.0 k
Figure 8. Output Voltage versus Frequency
Figure 9. Common Mode Rejection Ratio versus Frequency
PSRR, Power Supply Rejection Ratio (dB)
100 PSR + 80 60 40 20 0 10 PSR -
VS = 2.5 V RL = AV = 1.0 TA = 25C
|ISC|, Output Short Circuit Current (mA)
120
280 240 200 160 120 80 40 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 85C Output Pulsed Test at 3% Duty Cycle -40C 25C
100
1.0 k
10 k
100 k
1.0 M
10 M
f, Frequency (Hz)
VS, Supply Voltage (V)
Figure 10. Power Supply Rejection Ratio versus Frequency
Figure 11. Output Short Circuit Sinking Current versus Supply Voltage
|ISC|, Output Short Circuit Current (mA)
200 160 120 80 40 0
Output Pulsed Test at 3% Duty Cycle 25C
1.0 -40C |ID|, Supply Current (mA) 0.8 0.6 0.4 0.2 0 25C 85C -40C
85C
RL = AV = 1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VS, Supply Voltage (V)
VS, Supply Voltage (V)
Figure 12. Output Short Circuit Sourcing Current versus Supply Voltage
Figure 13. Supply Current versus Supply Voltage with No Load
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10 THD, Total Harmonic Distortion (%) AV = 1000 1.0 VS = 0.5 V Vout = 0.4 Vpp RL = 2.0 k TA = 25C AV = 100 AV = 10 THD, Total Harmonic Distortion (%) 10 AV = 1000 1.0 AV = 100 VS = 0.5 V Vout = 0.4 Vpp RL = 10 k TA = 25C AV = 10
0.1
0.1
AV = 1.0 0.01 10 100 1.0 k f, Frequency (Hz) 10 k 100 k
AV = 1.0 0.01 10 100 1.0 k f, Frequency (Hz) 10 k 100 k
Figure 14. Total Harmonic Distortion versus Frequency with 1.0 V Supply
Figure 15. Total Harmonic Distortion versus Frequency with 1.0 V Supply
10 THD, Total Harmonic Distortion (%) THD, Total Harmonic Distortion (%) AV = 1000 1.0 AV = 100 0.1 AV = 10 VS = 2.5 V Vout = 4.0 Vpp RL = 2.0 k TA = 25C 100 1.0 k f, Frequency (Hz) 10 k 100 k
10 AV = 1000 1.0 AV = 100 0.1 AV = 10 VS = 2.5 V Vout = 4.0 Vpp RL = 10 k TA = 25C 100 1.0 k f, Frequency (Hz) 10 k 100 k
0.01 AV = 1.0 0.001 10
0.01 AV = 1.0 0.001 10
Figure 16. Total Harmonic Distortion versus Frequency with 5.0 V Supply
Figure 17. Total Harmonic Distortion versus Frequency with 5.0 V Supply
1.5 1.4 SR, Slew Rate (V/ms) 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 -50 -Slew Rate, VS = 2.5 V +Slew Rate, VS = 0.5 V -Slew Rate, VS = 0.5 V RL = 10 k CL = 10 pF AV = 1.0 +Slew Rate, VS = 2.5 V GBW, Gain Bandwidth Product (MHz)
3.0 VS = 2.5 V RL = 10 k CL = 10 pF 2.0
1.0
-25
0
25
50
75
100
125
0 -50
-25
0
25
50
75
100
125
TA, Ambient Temperature (C)
TA, Ambient Temperature (C)
Figure 18. Slew Rate versus Temperature
Figure 19. Gain Bandwidth Product versus Temperature
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60 40 AV, Gain (dB) 20 0 VS = 2.5 V VS = 0.5 V VS = 2.5 V VS = 0.5 V RL = 100 k TA = 25C Amp = 0.8 mV 100 k 1.0 M f, Frequency (Hz) 10 M 60 100 140 180 100 Phase Margin Fm, Excess Phase () Am, Gain Margin (dB) Fm, Phase Margin () Fm, Phase Margin () Fm, Phase Margin () 80 60 40 20 0 -50 Gain Margin VS = 2.5 V RL = 10 k CL = 10 pF 80 60 40 20 0 125 100
-20
220 260 100 M
-40 10 k
-25
0
25
50
75
100
TA, Ambient Temperature (C)
Figure 20. Voltage Gain and Phase versus Frequency
Figure 21. Gain and Phase Margin versus Temperature
100 Phase Margin 80 60 40 20 0 VS = 2.5 V RL = 10 k CL = 10 pF TA = 25C Gain Margin
100 80 60 40 20 0 100 k
100 Phase Margin 80 60 40 Gain Margin 20 0 1.0 VS = 2.5 V RL = 10 k AV = 100 TA = 25C
100 80 60 40 20 0 1000
1.0
100 1.0 k 10 k 10 Rt, Differential Source Resistance (W)
Fm, Phase Margin () Am, Gain Margin (dB)
Am, Gain Margin (dB)
10 100 CL, CapacitIve Load (pF)
Figure 22. Gain and Phase Margin versus Differential Source Resistance
Figure 23. Gain and Phase Margin versus Output Load Capacitance
8.0 Vout, Output Voltage (Vpp)
100 Phase Margin 80 60 40 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0.5 1.0 1.5 2.0 2.5 3.0 VS, Supply Voltage (V) VS, Supply Voltage (V) Gain Margin
100 80 60 40 20 0 3.5
6.0
4.0
2.0
RL = 10 k AV = 100 TA = 25C
0
Figure 24. Output Voltage Swing versus Supply Voltage
Am, Gain Margin (dB)
Figure 25. Gain and Phase Margin versus Supply Voltage
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100 AVOL, Open Loop Voltage Gain (dB) 80 60 40 20 0 RL = 10 k TA = 25C VIO, Input Offset Voltage (mV) 20 15 10 5 0 -5 -10 -15 -20 -3.0 -2.0 -1.0 0 1.0 2.0 3.0 VS = 2.5 V RL = CL = 0 AV = 1.0 TA = 25C
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VS, Supply Voltage (V)
VCM, Common Voltage Range (V)
Figure 26. Open Loop Voltage Gain versus Supply Voltage
Figure 27. Input Offset Voltage versus Common Mode Input Voltage Range, VS = +2.5 V
20 VIO, Input Offset Voltage (mV) 15 10 5 0 -5 -10 -15 -20 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 VS = 0.9 V RL = CL = 0 AV = 1.0 TA = 25C
3.0 2.0 1.0 0 -1.0 -2.0 -3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 VS, Supply Voltage (V) D VIO = 5.0 mV RL = CL = 0 AV = 1.0 TA = 25C
VCM, Common Mode Input Voltage (V)
Figure 28. Input Offset Voltage versus Common Mode Input Voltage Range, VS = +0.9 V
VCM, Input Common Mode Voltage Range (V)
Figure 29. Common-Mode Input Voltage Range versus Power Supply Voltage
3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VS, Supply Voltage (V) RL = AV = 1.0 TA = 25C VEN, Enable Input Voltage (V)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VS, Supply Voltage (V) AV = TA = 25C VEN(off) VEN(on)
ICC, Supply Current (mA)
Figure 30. Supply Current versus Supply Voltage (Disabled)
Figure 31. Enable Input Voltage versus Supply Voltage
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16 14 Propagation Delay (mS) 12 10 8.0 6.0 4.0 2.0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 toff ton RL = 10 k TA = 25C
VS, SUPPLY VOLTAGE (V)
Figure 32. Propagation Delay versus Supply Voltage
APPLICATION INFORMATION AND OPERATING DESCRIPTION GENERAL INFORMATION The NCS2002 is an industry first rail-to-rail input, rail-to-rail output amplifier that features guaranteed sub one volt operation. This unique feature set is achieved with the use of a modified analog CMOS process that allows the implementation of depletion MOSFET devices. The amplifier has a 1.0 MHz gain bandwidth product, 1.2 V/ms slew rate and is operational over a power supply range less than 0.9 V to as high as 7.0 V. Inputs The input topology chosen for this device series is unconventional when compared to most low voltage operational amplifiers. It consists of an N-channel depletion mode differential transistor pair that drives a folded cascade stage and current mirror. This configuration extends the input common mode voltage range to encompass the VEE and VCC power supply rails, even when powered from a combined total of less than 0.9 volts. Figures 27, 28 and 29 show the input common mode voltage range versus power supply voltage. The differential input stage is laser trimmed in order to minimize offset voltage. The N-channel depletion mode MOSFET input stage exhibits an extremely low input bias current of less than 10 pA. The input bias current versus temperature is shown in Figure 4. Either one or both inputs can be biased as low as VEE minus 300 mV to as high as 7.0 V without causing damage to the device. If the input common mode voltage range is exceeded, the output will not display a phase reversal. If the maximum input positive or negative voltage ratings are to be exceeded, a series resistor must be used to limit the input current to less than 2.0 mA. The ultra low input bias current of the NCS2002 allows the use of extremely high value source and feedback resistor without reducing the amplifier's gain accuracy. These high value resistors, in conjunction with the device input and printed circuit board parasitic capacitances Cin, will add an additional pole to the single pole amplifier in Figure 33. If low enough in frequency, this additional pole can reduce the phase margin and significantly increase the output settling time. The effects of Cin, can be canceled by placing a zero into the feedback loop. This is accomplished with the addition of capacitor Cfb. An approximate value for Cfb can be calculated by:
Cfb + Rin Cin Rfb
Cfb Rfb Input Rin Cin - +
Output
Cin = Input and printed circuit board capacitance
Figure 33. Input Capacitance Pole Cancellation
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Output The output stage consists of complementary P and N channel devices connected to provide rail-to-rail output drive. With a 2.0 k load, the output can swing within 50 mV of either rail. It is also capable of supplying over 75 mA when powered from 5.0 V and 1.0 mA when powered from 0.9 V. When connected as a unity gain follower, the NCS2002 can directly drive capacitive loads in excess of 820 pF at room temperature without oscillating but with significantly reduced phase margin. The unity gain follower configuration exhibits the highest bandwidth and is most prone to oscillations when driving a high value capacitive load. The capacitive load in combination with the amplifier's output impedance, creates a phase lag that can result in an under-damped pulse response or a continuous oscillation. Figure 35 shows the effect of driving a large capacitive load in a voltage follower type of setup. When driving capacitive loads exceeding 820 pF, it is recommended to place a low value isolation resistor between the output of the op amp and the load, as shown in Figure 34. The series resistor isolates the capacitive load from the output and enhances the phase margin. Refer to Figure 36. Larger values of R will result in a cleaner output waveform but excessively large values will degrade the large signal rise and fall time and reduce the output amplitude. Depending upon the capacitor characteristics, the isolation resistor value will typically be between 50 to 500 W. The output drive capability for resistive and capacitive loads is shown in Figures 2, 3, and 23.
Input + - R Output CL
Isolation resistor R = 50 to 500
Figure 34. Capacitance Load Isolation
Note that the lowest phase margin is observed at cold temperature and low supply voltage. Enable Pin The enable pin allows the user to externally control the device. if the enable pin is pulled below the input disable threshold voltage (VEN < 45% VCC), the amplifier is disabled. Once the enable pin is taken above the threshold voltage (VEN = 60% VCC), the amplifier will turn on. In the event the enable pin is not connected, the amplifier will remain on by default
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NCS2002, NCV2002
Vin VS = 0.45 V Vin = 0.8 VPP R=0 CL = 820 pF AV = 1.0 TA = 25C
Vout
Figure 35. Small Signal Transient Response with Large Capacitive Load
Vin VS = 0.45 V Vin = 0.8 VPP R = 51 CL = 820 pF AV = 1.0 TA = 25C
Vout
Figure 36. Small Signal Transient Response with Large Capacitive Load and Isolation Resistor.
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RT 470 k Output Voltage 0.9 V CT 1.0 nF - + R1a 470 k R1b 470 k R2 470 k Timing Capacitor Voltage fO = 1.5 kHz
VCC 0 0.67 VCC 0.33 VCC
0.9 V
The non-inverting input threshold levels are set so that the capacitor voltage oscillates between 1/3 and 2/3 of VCC. This requires the resistors R1a, R1b and R2 to be of equal value. The following formula can be used to approximate the output frequency.
1 f+ O 1.39 R TC T Figure 37. 0.9 V Square Wave Oscillator
cww 1.0 M
10 k
D1 1N4148 Output Voltage
VCC 0
10 k cw CT 1.0 nF VCC - + R1a 470 k VCC R1b 470 k
D2 1N4148
Timing Capacitor Voltage
0.67 VCC 0.33 VCC Clock-wise, Low Duty Cycle VCC
Output Voltage fO 0 Timing Capacitor Voltage 0.67 VCC 0.33 VCC Counter-Clock-wise, High Duty Cycle R2 470 k The timing capacitor CT will charge through diode D2 and discharge through diode D1, allowing a variable duty cycle. The pulse width of the signal can be programmed by adjusting the value of the trimpot. The capacitor voltage will oscillate between 1/3 and 2/3 of VCC, since all the resistors at the non-inverting input are of equal value.
Figure 38. Variable Duty Cycle Pulse Generator
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R1 1.0 M
2.5 V + Cin 10 mF - -2.5 V R3 1.0 k 10,000 mF
R2 1.0 M
R Ceff. + 1 Cin R3
Figure 39. Positive Capacitance Multiplier
Cf 400 pF Rf 100 k
Af
fL R2 10 k Vin C1 80 nF 0.5 V + - R1 10 k -0.5 V
fH
1 f+ [ 200 Hz L 2pR C 11
VO
1 f+ [ 4.0 kHz H 2pRC ff R A + 1 ) f + 11 f R2
Figure 40. 1.0 V Voiceband Filter
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Vsupply
VCC Vin + -
I
V in + sink R sense
Rsense
Figure 41. High Compliance Current Sink
Is Rsense R1 1.0 k
VL
1.0 V R3 1.0 k
RL
R4 + - 1.0 k R5 2.4 k 75
Is VO R6 435 mA 212 mA
VO 34.7 mV 36.9 mV
R2 3.3 k
For best performance, use low tolerance resistors.
Figure 42. High Side Current Sense
ORDERING INFORMATION1
Device NCS2002SN1T1 NCS2002SN1T1G NCS2002SN2T1 NCS2002SN2T1G NCV2002SN1T1 NCV2002SN1T1G NCV2002SN2T1 NCV2002SN2T1G Marking P P Q Q P P Q Q Package TSOP-6 TSOP-6 (Pb-Free) TSOP-6 TSOP-6 (Pb-Free) TSOP-6 TSOP-6 (Pb-Free) TSOP-6 TSOP-6 (Pb-Free) Shipping
3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NCV2002: Tlow = -40C, Thigh = +125C. Guaranteed by design. NCV prefix is for automotive and other applications requiring site and change control.
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NCS2002, NCV2002
PACKAGE DIMENSIONS
TSOP-6 CASE 318G-02 ISSUE S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. DIM A A1 b c D E e L HE q MIN 0.90 0.01 0.25 0.10 2.90 1.30 0.85 0.20 2.50 0 MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 1.50 1.70 0.95 1.05 0.40 0.60 2.75 3.00 10 - MIN 0.035 0.001 0.010 0.004 0.114 0.051 0.034 0.008 0.099 0 INCHES NOM 0.039 0.002 0.014 0.007 0.118 0.059 0.037 0.016 0.108 - MAX 0.043 0.004 0.020 0.010 0.122 0.067 0.041 0.024 0.118 10
D
HE
6 1
5 2
4 3
E
b e c L q
0.05 (0.002) A1
A
SOLDERING FOOTPRINT*
2.4 0.094
1.9 0.075
0.95 0.037 0.95 0.037 0.7 0.028 1.0 0.039
SCALE 10:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCS2002/D

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